Logic Design and Verification Using SystemVerilog (Revised)

LOGIC PROGRAMMING WITH FLIX: BUILDING ANALYZERS AND CONSTRAINT SOLVERS: DESIGN STATIC ANALYZERS, TYPE CHECKERS, AND PROGRAM VERIFICATION TOOLS WITH DATALOG AND FUNCTIONAL PROGRAMMING ON THE JVM

LEAN PROGRAMMING FOR FORMAL SOFTWARE VERIFICATION: Mathematical proof systems and logical frameworks for verified computation

SystemVerilog for Hardware Description: RTL Design and Verification

Formal Verification: An Essential Toolkit for Modern VLSI Design